IMEC's Semiconductor Roadmap: Sub-1nm Nodes and Beyond

Sub-1nm process technologies won't arrive before 2034, according to IMEC's latest roadmap. The research center's projections for logic chip development from the 2020s through the 2040s confirm that Moore's Law remains alive, albeit advancing at a much slower pace than in the past.

The near-term focus is on nanosheet Gate-All-Around transistors, with the 2nm N2 node as the first major milestone. Beyond that, angstrom-class nodes such as A14 and A10 are on the horizon. It's important to note that these milestones indicate when the underlying technologies should be ready, not when finished products will ship.

Moving to sub-1nm manufacturing is penciled in for roughly 2034. The enabling innovation will be CFET transistors, which stack p- and n-channel structures on top of each other. The initial node in this family, designated A7 (0.7nm), would then be succeeded by A5 around 2036 and A3 by 2040.

Looking further ahead, the 2040s could bring 2D FET transistors built on novel materials. IMEC projects that these will underpin the A2 node (0.2nm) around 2043, with sub-0.2nm technologies possibly emerging by 2046. Of course, such long-range timelines are inherently speculative and subject to revision.

New transistor designs alone won’t sustain progress, of course. IMEC emphasizes the growing role of 2.5D and 3D packaging, chiplets, advanced interconnect materials, integrated voltage regulators, and smarter power delivery. Taken together, these building blocks are expected to drive the next wave of AI accelerators, high-performance computing systems, and future processors.