Samsung moves HBM above the AI accelerator and shows 400-layer V-NAND

Samsung has unveiled several next-generation memory and storage technologies at the Future of Memory and Storage event in Santa Clara. Most of the developments target data centers, AI accelerators and edge computing systems.

One of the main highlights was the zHBM concept. In this architecture, HBM is placed directly above the AI accelerator rather than beside it. Samsung estimates that this layout could deliver up to an eightfold performance increase over conventional designs. The company plans to manufacture zHBM with a next-generation wafer-bonding process. It is expected to provide more than ten times the memory density of HBM5 while tripling energy efficiency.

Samsung also showed V10 BV-NAND, a new type of vertical flash memory for solid-state drives, memory cards and other storage devices. The Bonding V-NAND architecture can combine more than 400 cell layers, raising density by about 58% over the V9 generation. The company also claims higher read, write and input/output performance.

Another development was zNAND-O, which combines efficient use of space, low latency and improved input/output performance. The solution is aimed primarily at edge AI systems.

The company also demonstrated LPDDR5X-PIM, Samsung’s first LPDDR5X memory with built-in processing-in-memory technology. It can perform some computations directly inside the memory, reducing data movement between components and improving overall system efficiency.