TSMC A16 (1.6nm) Process: Backside Power Delivery and Nanosheet Transistors

TSMC A16 Node: 1.6nm Angstrom-Era Chip with Super Power Rail
© D. Novikov

TSMC is gearing up to unveil its new A16 process—also referred to as 1.6-nm technology—which marks a significant early move into what the industry calls the angstrom era. More details will be shared at the 2026 VLSI Symposium, where the company is set to detail key advancements over its 2-nm generation.

The standout feature of A16 is backside power delivery. TSMC brands it Super Power Rail, or SPR. The approach is intended to free up the front side of the chip for signal connections, boost logic density, and reduce voltage drop, thereby enhancing power delivery efficiency. According to TSMC, the backside contact scheme preserves gate density, die area, and transistor width flexibility on par with traditional front-side power delivery.

A16 adopts refined nanosheet transistors, first seen in the N2 node. Compared to N2P, the new technology should enable an 8–10% speed improvement at the same voltage, or a 15–20% power reduction at the same performance. Chip density is claimed to increase by up to 1.10x, which includes gains in both logic and SRAM density.

TSMC believes A16 will be a strong fit for high-performance computing, given its complex signal routing and dense power grids. That positions the node as relevant for future HPC chips, AI accelerators, and other solutions that demand a mix of high performance, power efficiency, and tight integration.

Volume manufacturing of A16 is slated for the fourth quarter of 2026, though the first commercial products are likely to arrive later, in the 2027–2028 timeframe. The node joins a broader TSMC portfolio that includes A14, A13, and A12. A13 is envisioned as a die shrink of A14, offering roughly 6 percent area savings and entering production by 2029. A12, meanwhile, is set to be an extension of A14 incorporating Super Power Rail.

Advancing these nodes matters as demand for AI chips surges and TSMC expands its manufacturing capacity. Meanwhile, competitive pressure is mounting: Intel already employs backside power delivery in its 18A node and is pushing future nodes like 18A-P and 14A, along with advanced packaging such as EMIB. For TSMC, rolling out A16 represents an attempt to hold onto its lead in cutting-edge semiconductor technology in the next phase of the race.