Learn about Samsung's 1-nanometer process development, using fork technology to boost transistor density and energy efficiency for future mobile processors.
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Samsung is pushing forward with lithography technology, aiming to introduce a 1-nanometer process by 2031, which is being called the "dream semiconductor." Research and development efforts are currently underway and are expected to conclude by 2030. This new technology will enable more transistors to be packed into the same area through a "fork" method that adds a non-conductive barrier between GAA elements.
Current 2-nm processes from Samsung utilize Gate-All-Around (GAA) technology, which boosts energy efficiency by expanding channels from three to four lanes. In the 1-nm node, using GAA without modifications would be less effective, so the company is implementing a branching scheme with the "fork" to maximize transistor density. Essentially, this is akin to architectural densification in buildings: free space is reduced, and new structures occupy it to accommodate more components.
Previously, Samsung had planned a 1.4-nm process, but its release was postponed until 2028, likely to focus on advancing 2-nm technologies. The "fork" technology could address earlier production challenges, but the final efficiency and scalability of the 1-nm process will only become clear with the start of mass production.
Beyond this, Samsung continues to tackle energy efficiency issues in its SoCs, such as the Exynos 2600. For instance, this chip consumes up to 30 W during Geekbench 6 tests, which reduces device battery life compared to competitors using Snapdragon. Moving to enhanced 2-nm processes and eventually launching the 1-nm technology should help resolve these shortcomings and set the stage for future mobile processors.